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THIS DISCLAIMER APPLIES DESPITE ANY VERBAL REPRESENTATIONS OF ANY KIND PROVIDED BY ANY STRATUS EMPLOYEE OR REPRESENTATIVE. :display_atlantic_bus_meters.info Page &page_number& display_atlantic_bus_meters 6/13/93 Purpose This command estimates the utilization of the main bus. The main bus is the system bus that interconnects all of the major system boards. Display Form --------------------- display_atlantic_bus_meters ------------------- -cpu_slot: 30 -n_samples: 30 -delay: 50 -significance: 90 -module: %es#m18 -long: no Command Line Form display_atlantic_bus_meters [-cpu_slot number] [-n_samples number] [-delay number] [-significance string] [-module module_name] [-long] Arguments -cpu_slot number The backpanel slot number of one of the CPU boards. The default is slot 30. Any of the slots with an online CPU can be used. -n_samples number Specifies the number of measurements to take. The default is 30 samples. The minimum is 2 samples. The maximum is 300 samples. -delay number Specifies the number of milliseconds between the beginning of each measurement period. The default is 50 milliseconds. The minimum is 9 milliseconds. The maximum is 3,600,000 milliseconds (one hour). -significance string Cycle Specifies the level of significance desired in the calculation of the confidence interval. Possible values are 90, 95, 98, 99, 99.8, 99.98. The default is 90 per cent. -module module_name Specifies the module that is to be measured. By default, the command uses the current module. -long Displays each sample value and the confidence intervals. By default, only summary information is displayed. Explanation The display_atlantic_bus_meters command estimates main bus utilization. Utilization is defined as the percent of non-idle bus cycles. Since it relies on counters that exist only on the G861 and G862 processor models ("Atlantic" processors), it cannot be used on any other processor model. The hardware counters measure main bus utilization for a maximum of 65536 bus cycles (8.192 milliseconds). In order to get an accurate measurement, this command takes multiple measurements (samples) and pauses for a period of time (the delay time) between each measurement. You can control the number of samples with the -n_samples argument and can control the delay time with the -delay argument. Each sample requires 8.192 milliseconds. The command starts the hardware counters then waits. Thus, the delay time must be longer than 8.192 milliseconds; that is why the command enforces a minimum delay time of 9 milliseconds. Transactions on the main bus are often "bursty"; the load fluctuates with time. Therefore, this command takes multiple measurements by default, and includes the necessary statistical tests to display the "confidence interval" of the measurement. The program correctly calculates confidence intervals for 2 to 30 samples. If more than 30 samples are requested, all of the samples are used to calculate the average and standard deviation, but the confidence interval is calculated as if just 30 samples were taken. To get the most accurate results at least 30 samples should be taken. You can vary the delay time in order to average the measurements over a shorter or longer period, as appropriate. Because the hardware counters must be dedicated to this command, only one instance of this command can be used at the same time. The program enforces this restriction by permitting only one user to execute a given copy of the program at the same time. While this program can be used remotely, cross-network delays and additional system overhead will affect the measurement. You should run the program locally if possible. Access Requirements You must be privileged to use this command. Interpretation of Results An idle bus cycle is one that was not used by any board. An active bus cycle is one that was used. Active cycles can be useful (data was read or written) or busy (data was not read or written). The program calculates the per cent of the total bus cycles that were idle, useful and busy ("%total"). It also calculates the per cent of active bus cycles that were busy ("%activ"). Active cycles are used to transfer data between CPUs and main memory, or between I/O boards and main memory. Busy cycles occur because the memory is unable to access the desired location (a "wait state" is required) or because the desired location is not in main memory but is contained in the cache of a different Atlantic CPU. Memory wait states are rare on Freeway memories. Therefore, when Freeway memories are in use, busy bus cycles are an indication of the level of data sharing between Atlantic processors in a multiprocessor configuration. Since each busy cycle must be repeated, and since when it is repeated it (usually) will not be busy, the maximum number of active cycles that can be busy is 50%. (Under conditions of extremely heavy load, it is possible for a bus cycle to be busied multiple times before it succeeds). Busies can be issued for unencacheable data and for encacheable data. Unencacheable data is read and written as 64-bit quantities. Therefore, a busy cycle will force two additional bus cycles (first to write, then to re-read the desired location) beyond the one cycle that would have been required. Encacheable data is read and written as four 64-bit quantities (32 bytes). A busy can be issued on any of the four 64-bit locations. A busy on the first location (worst case) requires three consecutive busies followed by four cycles to store the cache line, followed by four cycles to re-read the cache line. This is a total of seven additional bus cycles beyond the four that would have been required. You can see that a busy bus cycle is only the tip of the iceberg. Each busy is an indication of from 2 to 2.3 additional bus cycles; all of which are counted as "useful" cycles by this command. Examples !display_atlantic_bus_meters Estimating main bus activity on module %es#m18, via the CPU in slot 30. Taking 30 measurements; one every 50 ms. 16.3% of the bus cycles were sampled. IDLE ACTIVE ============= ==================================== IDLE %total USEFUL %total BUSY %total %activ AVERAGE 59488 90.8 4186 6.4 1860 2.8 30.8 STD DEV 3288 2361 1048 Main bus utilization on %es#m18: 9.1% (7.6% to 10.7% with 90% probability.) !display_atlantic_bus_meters -n_samples 10 -long Estimating main bus activity on module %es#m18, via the CPU in slot 30. Taking 10 measurements; one every 50 ms. Start Time: 93-05-12 12:51:21 EDT Stop Time: 93-05-12 12:51:21 EDT 16.0% of the bus cycles were sampled. IDLE ACTIVE ============= ==================================== NUMBER IDLE %total USEFUL %total BUSY %total %activ 1 56972 86.9 5349 8.2 3215 4.9 37.5 2 62214 94.9 2176 3.3 1146 1.7 34.5 3 58923 89.9 4220 6.4 2393 3.7 36.2 4 63144 96.4 1628 2.5 764 1.2 31.9 5 60798 92.8 2968 4.5 1770 2.7 37.4 6 59886 91.4 3853 5.9 1797 2.7 31.8 7 59033 90.1 4266 6.5 2237 3.4 34.4 8 62426 95.3 2348 3.6 762 1.2 24.5 9 57898 88.3 5609 8.6 2029 3.1 26.6 10 60852 92.9 3150 4.8 1534 2.3 32.7 AVERAGE 60214 91.9 3556 5.4 1764 2.7 33.2 STD DEV 2034 1335 762 --- 90% CONFIDENCE LEVEL --- HALF CI 1179 774 442 LOW CB 59035 90.1 2782 4.2 1322 2.0 HIGH CB 61394 93.7 4330 6.6 2206 3.4 Main bus utilization on %es#m18: 8.0% (6.2% to 9.8% with 90% probability.) Note Bug vos-3998 orphans three 32-byte, type RB, blocks of wired heap per sample. By default, display_atlantic_bus_meters takes 30 samples. This means that about 3K bytes of wired heap are orphaned with each invocation of this command. VOS releases 11.8.2a, 12.1l, 12.1.1, 12.2, and 13.1 all contain the necessary bug fix. Until you are running a release with this fix, reduce the number of samples and run the command sparingly. (end)